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document no. u18170ee2v0ds00 data published: may 2008 v850e/pho3 32-bit single-chip microcontroller the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. ? nec electronics 2008 data sheet mos integrated circuit v850e/pho3 description the v850e/pho3 single-chip microcontroller devices make the performance gains attainable with 32- bit risc-based controllers available for embedded control applications. the v850e/pho3 devices provide an excellent combination of general purpose peripheral functions like serial communication interfaces, timers/counters,measurement and control functions, with dedicated motor control timers and full can network support. the integrated flexray? interface implements the flexray? network protocol. thus equipped, the v850e/pho3 product is ideally suited for automotive control and electric power steering (eps) applications. it is also an excellent choice for other applications where a combi- nation of sophisticated peripheral functions and can network support is required. ? 32-bit risc cpu with harvard architecture ? internal flash memory: 992 kb ? internal ram: 60 kb ? data flash: 32 kb ? operating clocks cpu frequency: 80 / 128mhz with pll factor 5 / 8 mainosc: operates on 16mhz crystal pll ratio: factor 5 flexray?: 80mhz ? i/o lines: 143 + 5 input only ? timers 10 ch 16-bit general purpose timer/counter 2 ch 16-bit timer/counter with motor control 2 ch 16-bit general purpose timer/counter with pwm function ? a/d converter: 2 x 10 channels 10 bit resolution ? flexray interface: 1 (2 channels) (protocol specification v2.1) ? can interface: 2 channel (afcan) ? serial interfaces: 7 channels - clocked serial: 2 channels (csib) - clocked serial: 2 channels (csie) - uartc: 3 channels ? dma: 8 channels ? random number generator ? aux. frequency output ? clock monitor ? power save mode: halt ? on chip debug: n-wire and non break debug interface ? power supply: 3.3v +/- 0.3v and 1.5v+/-10% (refer to related chapter) ? temperature range: package: -40c to +125c bare die: -40c to +150c ? package: 357 pin fpbga, 0.8 mm ball-pitch (20 20 mm) ordering information product name product family package flash ram pd70f3483f1(a2)-ja1 v850e/pho3 fpbga 20 20 mm 768 kb 60 kb pd70f3483w-car v850e/pho3 bare die 768 kb 60 kb pd70f3441f1(a2)-ja1 v850e/pho3 fpbga 20 20 mm 992 kb 60 kb pd70f3441w-car v850e/pho3 bare die 992 kb 60 kb feature
2 data sheet u18170ee2v0ds00 v850e/pho3 table of contents 1. electrical target specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.5.1 input/output level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5.2 pin leak current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.5.3 operation and halt mode supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.6 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.6.1 power supply turning on / interception timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6.2 reset and interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.6.3 external asynchronous memory access read timing . . . . . . . . . . . . . . . . . . . . . 12 1.6.4 external asynchronous memory access write timing . . . . . . . . . . . . . . . . . . . . . 14 1.6.5 clocked serial interface b (csib) characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 16 1.6.6 clocked serial interface e (csie) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.6.7 uartc timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.8 can timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.6.9 ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6.10 flash memory programming characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2. recommended soldering conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3. package drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4. revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3 data sheet u18170ee2v0ds00 v850e/pho3 1. electrical target specification 1.1 absolute maximum ratings t a = 25c, v ss15x = cv ss15 = v ss3x = av ss0,1 = 0v notes: 1. please do not exceed absolute maximum rating (max. +4.6v) of each power supply voltage. 2. total sum of all input and output currents of all pins. cautions: 1. cautions: 1. do not directly connect output (o r i/o) pins of ic products to each other, or to v dd , v ss , and gnd. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the abso- lute maximum ratings are not exceeded. the ratings and conditions shown below for dc characteristics and ac characteristics are within the range for normal operation and quality assurance. table 1-1: absolute maximum ratings parameter symbol conditions ratings unit supply voltage v dd15x -0.5 to +2.0 v cv dd15 -0.5 to +2.0 v v dd3x -0.5 to +4.6 v av dd -0.5 to +4.6 v input voltage v i the pin x1 is excluded. -0.5 to v dd3 +0.3 (note 1) v analog input voltage v in ani00 to ani09 ani10 to ani19 -0.3 to av dd +0.3 (note 1) v a/d converter av ref0,1 -0.3 to av dd +0.3 (note 1) v high level output current i oh for 1 pin 1 pin -4.0 ma total of all pins (note 2) total -100.0 ma low level output current i ol for 1 pin 1 pin 4.0 ma total of all pins (note 2) total 100.0 ma operating ambient temperature t a normal operating mode (package) -40 to +125 c nbd operation -40 to + 80 c flash programming mode, when flash memory is written. (package) -40 to +125 c operating junction temperature t j normal operating mode (bare die) -40 to +150 c flash programming mode, when flash memory is written. (bare die) -40 to +150 c storage temperature t stg in tray. -65 to +125 c off tray, mounted but not powered. -65 to + 150 c
4 data sheet u18170ee2v0ds00 v850e/pho3 1.2 capacitance t a = 25c v dd15 = cv dd15 = v dd3x = av dd = v ss15x = cv ss15 = v ss3x = av ss0,1 = 0v 1.3 operation conditions 1.4 oscillator characteristics figure 1-1: oscillator recommendations remark: values of capacitors c1? and c2? depend on used crystal and must be specified in coopera- tion with the crystal manufacturer. cautions: 1. external clock input is prohibited. 2. wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. ? place the oscillation circuit as close as possible to x1 and x2 pins. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. table 1-2: pin leak current parameter symbol conditions min. typ. max. unit input capacitance c i fc=1mhz 15 pf input/output capacitance c io all pins are at 0v excluding the pin that is measured. 15 pf output capacitance c o 15 pf table 1-3: operating conditions internal system clock frequency operating temperature (topt) power supply voltage 80mhz, 128mhz t a = -40 to +125c normal operating mode (package) vdd15x=cvdd15=1.5v0.15v vdd3x=3.3v0.3v t j = -40 to +150c normal operating mode (bare die) x1 x2 c1' c2 '
5 data sheet u18170ee2v0ds00 v850e/pho3 ? do not route the wiring near a signal line through which a high fluctuating cur- rent flows. ? always make the ground point of the oscillator capacitor the same potential as cv ss15 . ? do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. 1.5 dc characteristics 1.5.1 input/output level t a = -40 to +125c t j = -40 to +150c vdd15x = cvdd15 = 1.5v +/-10%, vdd3x = 3.3v +/- 0.3v, vss15x = cvss15 = vss3x = 0v table 1-4: operating conditions parameter symbol conditions min. typ. max. unit oscillation frequency f osc 16 mhz oscillation stabilization time t ost the oscillation stabilization time depends on the crystal and circuit and must be specified in cooperation with the crys- tal manufacturer. ensure that all conditions and tolerances of all components are considered for deter- mination of oscillation stabilization time: resistance value capacity value voltage temperature manufacturing range n/a n/a n/a pll lockup time pstc internal digital counter, counting with fosc (fx=fosc) frequency. 2 14 /fx s table 1-5: input/output level (1/2) parameter symbol conditions min. typ. max. unit input voltage, high v ih pal,pah,pdl,pdh,pcd,pcs, pcm,mode1,ddi,dms,dck 0.7v dd3 v dd3 +0.3 v p0,p1,p2,p3,p4,p5,p6,p7,p8, p9,p10,p11, adn_dbg,mode3, frxda,frxdb, sync,clk_dbg 0.7v dd3 v dd3 +0.3 v _drst, mode_dbg 0.75v dd3 v dd3 +0.3 v mode0,mode2, _reset 0.8v dd3 v dd3 +0.3 v
6 data sheet u18170ee2v0ds00 v850e/pho3 notes: 1. _drst, mode_dbg 2. max +/-2.5 ma x 20 of output current simultaneously. only the output port pins and the flexray outputs have to be considered. (the output pins of the deb ugger (nbd/dcu) are excluded). 1.5.2 pin leak current t a = -40 to +125c t j = -40 to +150c v dd15x = cv dd15 = 1.5v +/-10%, v dd3x = 3.3v +/- 0.3v, v ss15x = cv ss15 = v ss3x = 0v input voltage, low v il pal,pah,pdl,pdh,pcd,pcs, pcm,mode1,ddi,dms,dck -0.5 0.3v dd3 v p0,p1,p2,p3,p4,p5,p6,p7,p8, p9,p10,p11, adn_dbg,mode3, frxda,frxdb, sync,clk_dbg -0.5 0.3v dd3 v _drst, mode_dbg -0.5 0.3v dd3 v mode0,mode2, _reset -0.5 0.2v dd3 v output voltage, high v oh i oh =-2.5 ma (note 2) v dd3 -1.0 v i oh =-0.1 ma v dd3 -0.4 v output voltage, low v ol i ol =2.5ma (note 2) 0.8 v i ol =0.1ma 0.4 v build in pull down resistor r l note 1 10 50 120 k table 1-6: pin leak current parameter symbol conditions min. typ. max. unit input leakage cur- rent, high i lih v i =v dd3x all pins except for the below men- tioned 10.0 a v i =av dd ani00 to ani09, ani10 to ani19 3.0 a input leakage cur- rent, low i lil v i = 0v all pins except for the below men- tioned -10.0 a v i = 0v ani00 to ani09, ani10 to ani19 -3.0 a output leakage current, high i loh v o = v dd3x all pins 10.0 a output leakage current, low i lol v o = 0v all pins -10.0 a table 1-5: input/output level (2/2) parameter symbol conditions min. typ. max. unit
7 data sheet u18170ee2v0ds00 v850e/pho3 1.5.3 operation and halt mode supply current t a = -40 to +125c t j = -40 to +150c v dd15x = cv dd15 = 1.5v +/-10%, v dd3x = 3.3v +/- 0.3v, v ss15x = cv ss15 = v ss3x = 0v notes: 1. the port output current resulting from built-in pull-up or pull-down resistances is not included. 2. the typical value refers to ta = 25c, vdd15x = 1.5v and vdd3x = 3.3v table 1-7: power supply current parameter conditions symbol min. typ. (note 2) max. unit supply current (note 1) normal operation mode v dd15x , cv dd15 f xx = 128mhz i dd15 220 430 ma v dd15x , cv dd15 f xx = 80mhz i dd15 195 400 ma v dd3x i dd3 35 100 ma flash programming mode v dd15x , cv dd15 f xx = 128mhz i ddf15 230 450 ma v dd15x , cv dd15 f xx = 80mhz i ddf15 205 420 ma v dd3x i ddf3 60 100 ma halt mode v dd15x , cv dd15 f xx = 128mhz i ddh15 200 390 ma v dd15x , cv dd15 f xx = 80mhz i ddh15 180 365 ma
8 data sheet u18170ee2v0ds00 v850e/pho3 1.6 ac characteristics ac test input measurement points , ac test output measurement points load conditions caution: if the load capacitance exceeds 35 pf due to the circuit configuration, bring the load capacitance of the device to 35 pf or less by inserting a buffer or by some other means. measurement points v ih v il v ih v il measurement points v oh v ol v oh v ol dut cl = 35 pf
9 data sheet u18170ee2v0ds00 v850e/pho3 1.6.1 power supply turning on / interception timing t a = -40 to +125c t j = -40 to +150c v dd15x = cv dd15 = 1.5v +/-10%, v dd3x = 3.3v +/- 0.3v, v ss15x = cv ss15 = v ss3x = 0v table 1-8: turning on / interception timing parameter symbol conditions min. max. unit v dd15x to v dd3x t rli 01s v dd3x to v dd15x t ril 01s v dd15x to reset t rlr 0.5+t osc a a. t osc depends on the external oscillator's stabilization time, crystal type and circuit and should be specified / evaluated in cooperation with the oscillator manufacturer. ms v dd3x to reset t rir 0.5+t osc b b. t osc depends on the external oscillator's stabilization time, crystal type and circuit and should be specified / evaluated in cooperation with the oscillator manufacturer. ms v dd3x to mode3-0 t rim 0.2 ms mode3-0 to reset t rmr 0ns reset to mode3-0 t frm 0ns reset to v dd3x t fri 500 ns reset to v dd15x t frl 500 ns v dd3x to v dd15x t fli 01s v dd15x to v dd3x t fil 01s
10 data sheet u18170ee2v0ds00 v850e/pho3 figure 1-2: turning on / interception timing mode3-0 _reset (_drst) (av dd ) v dd3x (cv dd ) v dd15x 1.35v 3.0v 3.0v 1.35v t ril t rli t fli t fil t rir t rlr t fri t frl t rmr t frm v ih v ih v il v il v il t rim
11 data sheet u18170ee2v0ds00 v850e/pho3 1.6.2 reset and interrupt timing t a = -40 to +125c t j = -40 to +150c v dd15x = cv dd15 = 1.5v +/-10%, v dd3x = 3.3v +/- 0.3v, v ss15x = cv ss15 = v ss3x = 0v figure 1-3: reset and interrupt timing table 1-9: reset and interrupt timing parameter symbol conditions min. max. unit reset input low level width t wrsl except for power on 500 ns nmi input low level width t wnil (analog filter) 500 ns nmi input high level width t wnih (analog filter) 500 ns intpn input low level width t witl n=0,1 (analog filter) 500 ns n=2...13 (digital filter) sampling clock 5t ns intpn input high level width t with n=0,1 (analog filter) 500 ns n=2...13 (digital filter) sampling clock 5t ns t wrsl t wnil t wnih t witl t with /reset nmi intpn remark: n = 2 to13
12 data sheet u18170ee2v0ds00 v850e/pho3 1.6.3 external asynchronous memory access read timing t a = -40 to +125c t j = -40 to +150c v dd15x = cv dd15 = 1.5v +/-10%, v dd3x = 3.3v +/- 0.3v, v ss15x = cv ss15 = v ss3x = 0v table 1-10: external asynchronous memory access read timing remarks: 1. t: 1/f xx 2. i: number of idle states specified by bcc register 3. w as : number of waits specified by awc register w ah : number of waits specified by awc register 4. w d : number of waits specified by dwc0, dwc1 register; w d 1 5. w: number of waits due to external wait signal (wait) 6. n = 0, 2, 3, 4 parameter symbol min. max. unit data input set up time (vs. address) <10> t said (2 + w as + w ah + w d + w) t - 19 ns data input set up time (vs. csn , ben0-3 ) <10> t said (2 + w as + w ah + w d + w) t - 19 ns data input set up time (vs. rd ) <11> t srdid (1.5 + w d + w) t - 19 ns rd low level width <12> t wrdl (1.5 + w d + w) t - 6 ns rd high level width <13> t wrdh (0.5 + w as + i) t - 6 ns address, csn , ben0-3 rd delay time <14> t dard (0.5 + w as ) t - 8.2 ns rd address delay time <15> t drda i*t ns rd csn delay time <15?> t drdcs 0ns rd ben0-3 delay time <15??> t drdben 0ns data input hold time (vs. rd ) <16> t hrdid 0ns rd data output delay time <17> t drdod (1 + i + w as + w ah ) t - 8 ns wait set up time (vs. address, csn , ben0-3 ) < 31 > t saw (1 + w d + w + w as + w ah ) t - 19 ns wait hold time (vs. address, csn , ben0-3 ) <32> t wwh (1 + w d + w + w as + w ah ) t - 3 ns
13 data sheet u18170ee2v0ds00 v850e/pho3 figure 1-4: external asynchronous memory access read timing figure 1-5: external asynchronous memory access read timing with idle cycle <15>,<15?>,<15??> <15>,<15?>
14 data sheet u18170ee2v0ds00 v850e/pho3 1.6.4 external asynchronous memory access write timing t a = -40 to +125c t j = -40 to +150c v dd15x = cv dd15 = 1.5v +/-10%, v dd3x = 3.3v +/- 0.3v, v ss15x = cv ss15 = v ss3x = 0v table 1-11: external asynchronous memory access write timing remarks: 1. t: 1/f xx 2. i: number of idle states specified by bcc register 3. w as : number of waits specified by awc register w ah : number of waits specified by awc register 4. w d : number of waits specified by dwc0, dwc1 register; w d 1 5. w: number of waits due to external wait signal (wait) 6. n = 0, 2, 3, 4 parameter symbol min. max. unit address, csn , ben0-3 wr delay time <20> t dawr (1 + w as + w ah )t - 5 ns wr bus output delay time <33> t dwrod1 0ns wr data output delay time <34> t dwrod2 5ns wr data float delay time <35> t fwrod 0.5t+3 ns address, csn , ben0-3 set up (vs. wr ) <21> t sawr (1.5 + w as + w ah + w d + w) t - 7 ns wr address delay time <22> t dwra (0.5 + i) t - 3 ns wr csn delay time <22?> t dwrcs 0.5 t - 3 ns wr ben0-3 delay time <22??> t dwrben 0.5 t - 3 ns wr high level width <23> t wwrh (1.5 + i + w as + w ah ) t - 6 ns wr low level width <24> t wwrl (0.5 + w + w d ) t - 6 ns data output set up time (vs. wr ) <25> t sodwr (0.5 + w d + w) t -5 ns data output hold time (vs. wr ) <26> t hwrod 0.5 t - 6 ns wait set up time (vs. address, csn , ben0-3 ) <31> t saw (1 + w d + w + w as + w ah )t - 19 ns wait hold time (vs. address, csn , ben0-3 ) <32> t wwh (1 + w d + w + w as + w ah )t - 3 ns
15 data sheet u18170ee2v0ds00 v850e/pho3 figure 1-12: external asynchronous memory access write timing a0-21
16 data sheet u18170ee2v0ds00 v850e/pho3 1.6.5 clocked serial interface b (csib) characteristics t a = -40 to +125c t j = -40 to +150c v dd15x = cv dd15 = 1.5v +/-10%, v dd3x = 3.3v +/- 0.3v, v ss15x = cv ss15 = v ss3x = 0v the load capacity of the output terminal is cl=35pf. table 1-13: csib characteristics (master mode) table 1-14: csib characteristics (slave mode) remark: n = 0, 1 cbncks2 to cbncks0 111b parameter symbol min. max. unit sckbn cycle time t cyskm 125 ns sckbn high level width t wskhm 0.5 t cyskm - 10 ns sckbn low level width t wsklm 0.5 t cyskm - 10 ns sibn setup time t ssiskm 20 ns sibn hold time t hsksim 10 ns sobn delay t dsksom 10 ns sobn hold time t hsksom 0.5 t cyskm - 10 ns cbncks2 to cbncks0 = 111b parameter symbol min. max. unit sckbn clock cycle time t cysks 125 ns sckbn high level width t wskhs 0.5 t cysks - 10 ns sckbn low level width t wskls 0.5t cysks - 10 ns sibn setup time t ssisks 5ns sibn hold time t hsksis 10 ns sobn delay t dsksos 25 ns sobn hold time t hsksos t wskhs ns
17 data sheet u18170ee2v0ds00 v850e/pho3 figure 1-15: csib master/slave mode timing t ssisk t hsksi t cysk t wskl t wskh t dskso output data input data so si sck t hskso
18 data sheet u18170ee2v0ds00 v850e/pho3 1.6.6 clocked serial interface e (csie) timing t a = -40 to +125c t j = -40 to +150c v dd15x = cv dd15 = 1.5v +/-10%, v dd3x = 3.3v +/- 0.3v, v ss15x = cv ss15 = v ss3x = 0v the load capacity of the output terminal is cl=35pf. table 1-16: csie characteristics (master mode) parameter symbol min. max. unit macro operation clock, cycle time t kcy 31.25 ns scken cycle time t kcym 125 ns scken high, low width t kwhm, t kwlm t kcym /2 - 10 ns sien input setup time (vs. scken )t ssim 20 ns sien input hold time (vs. scken )t hsim 10 ns soen output delay (vs. scken )t dsom 10 ns soen output hold time (vs. scken )t hsom t kcym /2 - 10 ns scsenm inactive (high) width censit=x cenope=0 cenmd=x t wscsb0 t kcym /2 - 10 ns censit=x cenope=1 cenmd=x t wscsb1 (cs idle + 0.5)*t kcym - 10 ns scsenm setup time (vs. scken ) censit=x cenope=0 cenidl=x cenmd=0 t sscsb0 t kcy - 10 ns censit=x cenope=1 cenidl=0 cenmd=0 t sscsb1 cs setup *t kcym + t kcy - 10 ns censit=x cenope=1 cenidl=1 cenmd=1 t sscsb2 cs setup *t kcym + t kcy - 10 ns
19 data sheet u18170ee2v0ds00 v850e/pho3 remark: n=0,1 m=7-0(n=0),3-0(n=1) cs setup ,cs inter : are set by register cenopt0 cs idle ,cs hold : are set by register cenopt1 table 1-17: csie characteristics (slave mode) remark: n=0,1 scsenm hold time (vs. scken ) censit=0 cenope=0 cenmd=x t hscsb0 t kcy - 10 ns censit=1 cenope=0 cenmd=x t hscsb1 t kcym /2 - 10 ns censit=0 cenope=1 cenmd=x t hscsb2 cs hold *t kcym - 10 ns censit=1 cenope=1 cenmd=x t hscsb3 (cs hold + 0.5)* t kcym - 10 ns scsenm interframe time censit=x cenope=1 cenmd=x t inter cs inter *t kcym ns censit=x cenope=0 cenmd=x - not applicable ns parameter symbol min. max. unit macro operation clock, cycle time t kcy 31.25 ns scken cycle time t kcys 125 ns scken high, low width t kwhs, t kwls t kcys /2 - 10 ns sien input setup time (vs. scken )t ssis 10 ns sien input hold time (vs. scken )t hsis t kcy *1.5 + 10 ns soen output delay (vs. scken )t dsos 20 ns soen output hold time (vs. scken )t hsos t kcys /2 - 10 ns table 1-16: csie characteristics (master mode) parameter symbol min. max. unit
20 data sheet u18170ee2v0ds00 v850e/pho3 figure 1-18: csien timings (a) [ scken /sien/soen] pins in master mode: (cenctl1: cenckp/cendap=0/0 or 1/1) remark: n=0-1 (b) [ scken /sien/soen] pins in master mode: (cenctl1: cenckp/cendap=1/0 or 0/1) remark: n=0-1 scken soen sien clock scken soen sien
21 data sheet u18170ee2v0ds00 v850e/pho3 (c) [ scken /sien/soen] pins in slave mode: (cenctl1: cenckp/cendap=0/0 or 1/1) remark: n=0-1 (d) [ scken /sien/soen] pins in slave mode: (cenctl1: cenckp/cendap=1/0 or 0/1) remark: n=0-1 scken scken
22 data sheet u18170ee2v0ds00 v850e/pho3 figure 1-19: csen7 - csen0 pin timings (e) only in master mode (cenctl0:censit=0 & cenctl4:cenope/cenmd=0/0) remark: n=0-1 m=7-0(n=0),3-0(n=1) intcenc: csien transfer end interrupt (f) only in master mode (cenctl0:censit=0 & cenctl4:cenope/cenmd=1/0) remark: n=0-1 m=7-0(n=0),3-0(n=1) intcenc: csien transfer end interrupt continuous transfer start intcenc scken intcenc
23 data sheet u18170ee2v0ds00 v850e/pho3 (g) only in master mode (cenctl0:censit=0 & cenctl4:cenope/cenmd=1/1) remark: n=0-1 m=7-0(n=0),3-0(n=1) intcenc: csien transfer end interrupt (h) only in master mode (cenctl0:censit=1 & cenctl4:cenope/cenmd=0/0) remark: n=0-1 m=7-0(n=0),3-0(n=1) intcenc: csien transfer end interrupt intcenc intcenc
24 data sheet u18170ee2v0ds00 v850e/pho3 (i) only in master mode (cenctl0:censit=1 & cenctl4:cenope/cenmd=1/0) remark: n=0-1 m=7-0(n=0),3-0(n=1) intcenc: csien transfer end interrupt (j) only in master mode (cenctl0:censit=1 & cenctl4:cenope/cenmd=1/1) remark: n=0-1 m=7-0(n=0),3-0(n=1) intcenc: csien transfer end interrupt intcenc intcenc
25 data sheet u18170ee2v0ds00 v850e/pho3 1.6.7 uartc timing t a = -40 to +125c t j = -40 to +150c v dd15x = cv dd15 = 1.5v +/-10%, v dd3x = 3.3v +/- 0.3v, v ss15x = cv ss15 = v ss3x = 0v the load capacity of the output terminal is cl=35pf. 1.6.8 can timing t a = -40 to +125c t j = -40 to +150c v dd15x = cv dd15 = 1.5v +/-10%, v dd3x = 3.3v +/- 0.3v, v ss15x = cv ss15 = v ss3x = 0v the load capacity of the output terminal is cl=35pf. figure 1-22: can timing notes: 1. the fcan internal clock corresponds to the fcan macro clock. table 1-20: uartc timing parameter symbol conditions min. max. unit transfer rate t uartc 4mbps table 1-21: can timing parameter symbol conditions min. max. unit internal transmit to receive data delay t node t node = t output + t input 75 ns f can in ternal clock note 1 ctx dn (n=0-3) pin (transfer da ta) crxdn (n=0-3) pin (rec eive da ta) t input t output
26 data sheet u18170ee2v0ds00 v850e/pho3 figure 1-23: internal delay this product can macro image figure of internal delay crxdn pin (n=0-3) internal receive delay internal transfer delay ctxdn pin (n=0-3) { {
27 data sheet u18170ee2v0ds00 v850e/pho3 1.6.9 ad converter t a = -40 to +125c t j = -40 to +150c vdd15x = cvdd15 = 1.5v +/- 10%v, vdd3x = 3.3v +/- 0.3v, avdd = avref0,1 = 3.3v +/- 0.3v, vss15x = cvss15 = vss3x = 0v, table 1-24: ad converter parameter symbol conditions min. typ. max. unit resolution 10 bit overall error a a. the quantization error is not included. notes: 1. the conversion time is set by the admn1 register. for admn1 register setting please refer to the users manual. 2. the conversion time only in the analog part. the conversion time depends on register set- ting admn1. for admn1 register setting please refer to the users manual. toe +/-4 lsb quantisation error +/-0.5 lsb conversion time (note 2) t conv 2.0 8.0 s sampling time t samp (note 1) 3 x t conv / 16 s analog input voltage v ian av ss0,1 av ref0,1 v av refn input voltage av ref0,1 av ref0,1 = av dd av dd v av refn input current ai ref0,1 60 300 a av dd electric current ai dd 6ma
28 data sheet u18170ee2v0ds00 v850e/pho3 1.6.10 flash memory programming characteristics (1) basic characteristics t a = -40 to +125c t j = -40 to +150c vdd15x = cvdd15 = 1.5v +/- 10%v, vdd3x = 3.3v +/- 0.3v, avdd = avref0,1 = 3.3v +/- 0.3v, vss15x = cvss15 = vss3x = 0v, the load capacity of the output terminal is cl=35pf. (2) serial writing operating conditions t a = -40 to +125c t j = -40 to +150c vdd15x = cvdd15 = 1.5v +/- 10%v, vdd3x = 3.3v +/- 0.3v, avdd = avref0,1 = 3.3v +/- 0.3v, vss15x = cvss15 = vss3x = 0v, the load capacity of the output terminal is cl=35pf. notes: 1. please consider also the power supply turning on to reset release timing. table 1-25: flash programming characteristics parameter symbol conditions min. typ. max. unit operating frequency f xx 80 128 mhz high level input voltage vih flmd0 0.7 vdd3x vdd3x low level input voltage vil flmd0 -0.5 0.3 vdd3x code flash reprogramming 100 times data retention 15 years data flash reprogramming 10000 times data retention 3 years table 1-26: serial writing characteristics parameter symbol conditions min. typ. max. unit flmd0 setup time (from vdd) t dp 1ms reset release (from flmd0) t pr (note 1) 2 ms count start time from reset to flmd0 f rp 1.2 ms count finish time from reset to flmd0 f rpe 10 ms flmd0 high / low level width t pw 10 100 s flmd0 raise / fall time t r / t f 1s
29 data sheet u18170ee2v0ds00 v850e/pho3 figure 1-27: serial write operation timing gnd vih tpw tpw trp vdd flmd0 _ reset tpr vdd flmd1 0v vdd gnd vdd gnd vdd gnd tf tr vil vih tdp vih trpe
30 data sheet u18170ee2v0ds00 v850e/pho3
31 data sheet u18170ee2v0ds00 v850e/pho3 2. recommended soldering conditions solder this product under the following recommended conditions. for details of the recommended soldering conditions, refer to the joint industry standard: jedec j-std-020c (msl=3) for soldering methods and conditions other than those recommended please consult nec.
32 data sheet u18170ee2v0ds00 v850e/pho3 [memo]
33 data sheet u18170ee2v0ds00 v850e/pho3 3. package drawings figure 3-1: pd70f3483f1(a2)-ja1, pd70f3441f1(a2)-ja1
34 data sheet u18170ee2v0ds00 v850e/pho3 [memo]
35 data sheet u18170ee2v0ds00 v850e/pho3 4. revision history table 4-1: revision history version date remarks. 1.0 2006/05/31 initial revision 1.1 2007/07/05 i dd currents for 80 mhz added (table 1-7 on page 7) revision history added adjusted min timings for trlr and trir flash characteristics added added special storage temperature changed naming from cv dd to cv dd15 added reset timing nbd operating temperature added junction temperature for bare die added external asynchronous memory access timing updated csib timing updated csie slave mode, formula of t hsis corrected csie master mode, formula of t sscsb2 corrected turning on / interception timing modified package drawing, parameters a and a1, updated. 2.0 2008/05/19 pd70f3483 added temperature range for bare die added msl for soldering conditions added
36 data sheet u18170ee2v0ds00 v850e/pho3 [memo]
37 data sheet u18170ee2v0ds00 v850e/pho3 notes for cmos devices 1. precaution against esd for semiconductors strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2. handling of unused input pins for cmos no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3. status before initialization of mos devices power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
38 data sheet u18170ee2v0ds00 v850e/pho3 legal notes ? the information in this document is current as of may 2008. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all prod- ucts and/or types are available in every country. please check with an nec sales representative for availability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. ? nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such nec electronics products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellec- tual property rights of nec electronics or others. ? descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorpora- tion of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and informa- tion. ? while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be elimi- nated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. ? nec electronics products are classified into the following three quality grades: ?standard?, ?special? and ?specific?. the "specific" quality grade applies only to nec electronics products developed based on a customer-designated ?quality assurance program? for a specific application. the recommended applications of nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is ?standard? unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact nec electronics sales representative in advance to determine nec electronics 's willingness to support a given application. notes: 1. "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. 2. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). 3. superflash ? is a registered trademark of silicon storage technology, inc. in several coun- tries including the united states and japan. this product uses superflash ? technology licensed from silicon storage technology, inc.
39 data sheet u18170ee2v0ds00 v850e/pho3 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and com- ponents, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa?a madrid, spain tel: 091- 504 27 87 fax: 091- 504 28 60 succursale fran?aise vlizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. singapore tel: 65-6253-8311 fax: 65-6250-3583 nec electronics taiwan ltd. ta i p e i , ta i wa n tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos, brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829
40 data sheet u18170ee2v0ds00 v850e/pho3 [memo]
41 data sheet u18170ee2v0ds00 v850e/pho3 although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-2719-5951 address north america nec electronics america inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh market communication dept. fax: +49(0)-211-6503-1344 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-6250-3583 japan nec semiconductor technical hotline i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 99.1 name company from: tel. fax facsimile message fax: +81- 44-435-9608
42 data sheet u18170ee2v0ds00 v850e/pho3 [memo]

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